fosstodon.org is one of the many independent Mastodon servers you can use to participate in the fediverse.
Fosstodon is an invite only Mastodon instance that is open to those who are interested in technology; particularly free & open source software. If you wish to join, contact us for an invite.

Administered by:

Server stats:

9.9K
active users

#ez80

0 posts0 participants0 posts today

Working on making my telnet for #AgonLight more sane, it's a little better than it was but still has a lot of problems. It's hard to test something when the results depend on the network traffic flow at the time, and many components out of my control. Anyway, for a first time I did manage to get some almost readable data from @Wintermute_BBS RC BBS - thanks for having this running! It feels awesome having an #ez80 talking to a #z80 on the other side of the world!

Small Update:

I got the TN-VDP working in 40 and 80 columns and just today I figured out how to get the Vsync interrupts working on my eZ80 board.
The rev2 board will include some changes. Of course I have reversed the data bits, and I also added a diode to the INT pin to make it compatible with an open-collector type bus.

I am very pleased with the speed so far. at 36 MHz, I can drive it with an IO cycle time of only 200ns, equating to 4.8 MHz

Got my Agon Light 2 computer recently and installed CP/M on it (github.com/julian-rose/Agon-CP). Great little machine, I am surprised how fast it is.
It self-compiles #T3X 16 times faster than a 4MHz Z80 (and clock speed is "only" 5 times faster). It even runs Evazor smoothly! I have added a CP/M binary to the Evazor archive in case you want to try it.
t3x.org/t3x/0/programs.html#ev
#agonlight, #retrocomputing, #CPM, #eZ80

Attempting a rewrite of my 8-bit multi-platform, multi-ISA, assembler's instruction parser. #v80 uses a static tree for mapping instructions into opcodes (2nd image) which is very fast and efficient but hairy to write.

The new approach (1st image), uses an alphabetical list of instructions with a byte to state how many chars of the previous entry are re-used since alphabetically, the left-most chars repeat the most.

There's no guarantee this will even save space (#Z80 ISA is currently 4KB, #MOS6502 is about 1.7KB) and it will likely be slower as more lines will need to be skipped vs. a char-by-char branching approach, but it may help for very large ISAs, the size of which can balloon drastically with lots of shared prefixes, something I'm worried about with adding #eZ80 support. The alternative is adding 'macro' characters for shared-prefixes, but that bloats the native code that needs to be ported between architectures.

Finally!
After ~12 hours more testing and debugging, I got CP/M 3 fully booted and working.
It took me quite a while to determine the proper wait states and timings for accessing the bank registers.
Now it boots up without any issue and I couldn't find any errors so far.

Today I found a really annoying glitch in my circuit with the eZ80.

I am using some inverters and an 74ACT139 to adress the 4 bank registers. What happens is:

When the eZ80 is done writing to the register, it immediately reads the next instruction. But the decode logic takes a couple of nanoseconds to detect that and release the write signal to the register. And during those few nanoseconds, the incrementing address causes the next bank register to be written with invalid data.