Habr<p>Chisel вместо Verilog, искажение тактового дерева и прототипирование ASIC: прокачиваем FPGA-скилы новыми темами</p><p>Осенью мы в</p><p><a href="https://habr.com/ru/companies/yadro/articles/870386/" rel="nofollow noopener" translate="no" target="_blank"><span class="invisible">https://</span><span class="ellipsis">habr.com/ru/companies/yadro/ar</span><span class="invisible">ticles/870386/</span></a></p><p><a href="https://zhub.link/tags/chisel" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>chisel</span></a> <a href="https://zhub.link/tags/system_verilog" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>system_verilog</span></a> <a href="https://zhub.link/tags/%D0%BF%D0%BB%D0%B8%D1%81" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>плис</span></a> <a href="https://zhub.link/tags/riscv" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>riscv</span></a> <a href="https://zhub.link/tags/asic" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>asic</span></a> <a href="https://zhub.link/tags/soc" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>soc</span></a> <a href="https://zhub.link/tags/embedded_linux" class="mention hashtag" rel="nofollow noopener" target="_blank">#<span>embedded_linux</span></a></p>