The Spade Hardware Description Language https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #HardwareDescriptionLanguage #SpadeLanguage #hardware #verilog #FPGA #ASIC #fpga #vhdl #hdl

The Spade Hardware Description Language - Spade is an open-source hardware description language (HDL) developed at Linköping... - https://hackaday.com/2025/04/13/the-spade-hardware-description-language/ #hardwaredescriptionlanguage #spadelanguage #hardware #verilog #fpga #asic #vhdl #hdl

Network Meta-Analysis of Metabolic Effects of Olive-Oil in Humans Shows the Importance of Olive Oil Consumption With Moderate Polyphenol Levels as Part of the Mediterranean Diet https://www.diningandcooking.com/2002898/network-meta-analysis-of-metabolic-effects-of-olive-oil-in-humans-shows-the-importance-of-olive-oil-consumption-with-moderate-polyphenol-levels-as-part-of-the-mediterranean-diet/ #cholesterol #glucose #hdl #Mediterranean #MediterraneanDiet #MediterraneanOliveOil #metabolism #Olive #OliveOil #polyphenols

Check out @dutracgi 's very cool #16APSK #FPGA Modulator written in #PipelineC #HDL !
#dsp #sdr #rf #apsk #dac #deltasigma #space #qam #radio #hardware https://www.linkedin.com/pulse/16-apsk-modulator-fpga-using-pipelinec-hdl-paulo-dutra-79uce/?trackingId=ldQbwhDmRd%2BU7F35jVGjAQ%3D%3D

#HDL hell, chapter in/out:

```
SI_SPI_DIN: out std_logic;
SI_SPI_DOUT: in std_logic;

CLK_DIV_SPI_DI: out std_logic;
CLK_DIV_SPI_DO: in std_logic;
```

Yay those cheap #hardware #ethernet phy #pmod -LIKE things work with the pico-ice #ice40 #FPGA . Thanks for your help with RMII interface @dutracgi ! #embedded #HDL #RTL #Verilog #VHDL #HLS https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/ethernet_top.c

Exciting update for the ROHD community! We're pleased to announce the release of ROHD Cosim v0.3.0, now supporting in/out ports and Verilator for enhanced simulation. Also, ROHD v0.6.2 is out, featuring some bug fixes and improved adder syntax in SystemVerilog. https://buff.ly/3WLth4y #rohd #opensource #hardware #hdl #cosim #verilator

Hi, I’m Max! I’m an engineer passionate about both hardware & software. I'm a Principal Engineer at Intel helping to shape the future of hardware, and I lead the open-source ROHD project, making hardware development more accessible and fun.

I enjoy working on personal projects (especially with Dart), snowboarding , gaming , and exploring new tech.

Excited to connect with folks in open-source, hardware, and beyond!

Come learn some PipelineC #HDL basics featuring the pico-ice dev board from tinyVision.ai! It has a Lattice Semiconductor @latticesemi #ice40 #FPGA and @Raspberrypi. This intro talk will cover #LED, #UART, and #VGA projects using OSS CAD Suite tools. #hardware #RTL #Verilog #VHDL #HLS

#Xilinx could have had a PERFECTLY FINE VALID-READY INTERFACE if it wasn't for that IMPORTANT note WHY! GAH! #hardware #FPGA #HDL #RTL #Verilog #VHDL

In the mood for the littlest bit of #FPGA #GameDev? Check out this pico-ice based #pong demo. Just need #VGA #pmod and #UART connected to host PC. #HDL #hardware #RTL #Verilog #VHDL #HLS #lattice #ice40 https://github.com/JulianKemmerer/PipelineC/blob/master/examples/pico-ice/ice_makefile_pipelinec/pong_top.c

Gifted a new #FPGA dev board this season? PipelineC aims to make #hardware description easier for #embedded folks.
Check out the new getting start page. Happy to help you get going! #hdl #verilog #vhdl #HLS
https://github.com/JulianKemmerer/PipelineC/wiki/Dev-Board-Setup

Xschem is a schematic capture program, it allows to create a hierarchical representation of circuits with a top down approach . By focusing on interconnections, hierarchy and properties a complex system (IC) can be described in terms of simpler building blocks. A VHDL, Verilog or Spice netlist can be generated from the drawn schematic, allowing the simulation of the circuit.
https://sourceforge.net/projects/xschem/

Lispy gopher climate #podcast coming up in two hours (at 000UTC Wednesday, aka Tuesday night for many).
https://anonradio.net/
Building a date prompt from my conference talk #mcclim #commonLisp
Hooking that to an #emacs #hook, my workaround.
Drawing inspiration from @kickingvegas' #casual (#emacsconf)

#lispCurse and @fosskers' transducers ; the little known counter-narrative evolution of the #lisp curse

Lisp Machine Revolution @amszmidt looking for #HDL + lisp collaborators.

#eevel mode ?

Have been super pleased with the #ice40 #FPGA and #raspberrypi board that https://pico-ice.tinyvision.ai/ sent me to experiment with. Many thanks and I look forward to putting together a talk for intro users getting started with #PipelineC and boards like the pico-ice #HDL #Verilog #VHDL #hardware #embedded